/*
 * @Description  : the general purpose register(register file) of cpu
 * @authorName   : GuoJi
 * @github       : https://github.com/guoji-kk
 * @gitee        : https://gitee.com/guoji13663585559
 * @email        : 13663585559@163.com
 * @version      : 1.0
 * @Date         : 2023-05-14 23:34:46
 * @LastEditTime : 2023-05-16 20:23:03
 */


module gpr(RegWr,ra,rb,rw,busW,clk,rst,busA,busB,Data_in); //RegFile
	input clk,rst,RegWr;
  	input [31:0]busW;
  	input [4:0]ra,rb,rw;
  	output [31:0]busA,busB,Data_in;
  
  	reg [31:0]regi[31:0]; //32regs of 32bits
  
  	//reset
	//TODO: only use in sim 
  	integer i;
  	always@(negedge rst)begin
    		if(!rst)
      			for(i=0;i<32;i=i+1)
      			regi[i]=0;
    	end
    
  	//set busA & busB
  	assign busA=regi[ra]; //rs
  	assign busB=regi[rb]; //rt
  	assign Data_in=busB;
  
  	//Register write in
  	always@(posedge clk)begin
    		if(RegWr)begin
      			regi[rw]<=busW; //busW->RWreg
      			regi[0]<=0;     //zero reg
    		end
  	end

endmodule
